1. Field of the Invention
The present invention relates to a solid-state image pickup device (apparatus) which features low noise and fast operation.
2. Related Background Art
FIG. 1 is a schematic circuit diagram which shows the overall configuration of a general image pickup device (including the case of an amplifying type image pickup device). In the image pickup device shown in FIG. 1, for the purpose of the description to follow, the example shown is that of a 2-row-by-2-column matrix of 4 pixels, in which MOS static induction transistors (hereinafter referred to as MOSSITs or simply SIT transistors) S.sub.101, S.sub.102 S.sub.201, and S.sub.202 are used in a source-follower type signal reading system.
The sources of each of the SIT transistors S.sub.101, S.sub.102 S.sub.201, and S.sub.202 are connected in common to a vertical source lines (vertical read-out lines) 2a and 2b of each of columns of the matrix arrangement, the drains thereof being connected in common to the power supply voltage VDS. Each of the gate electrodes of the SIT transistors S.sub.101, S.sub.102 S.sub.201, and S.sub.202 are connected to the clock lines 20a and 20b, which are scanned by the vertical scanning circuit 4 for each of the rows in the matrix arrangement, the voltage drive pulses .PHI.G1 and .PHI.G 2, which are sent by the vertical scanning circuit 4, providing drive in units of rows.
The vertical source lines 2a and 2b each have one end connected, via capacitors CS.sub.1 and CS.sub.2 for light signal output storage and via capacitors CD.sub.1 and CD.sub.2 for dark output storage, to MOS transistors TS.sub.1 and TS.sub.2, which are for transmitting an light signal output and to MOS transistors TD.sub.1 and TD.sub.2, which are for transmitting a dark output. These capacitors CS.sub.1, CS.sub.2, CD.sub.1, and CD.sub.2 are connected, via horizontal read selection MOS transistors TH.sub.S1, TH.sub.S2, TH.sub.D1, and TH.sub.D2, to the signal output line (horizontal read line) 16a and dark output line (horizontal read line) 16b.
In general, the signal output line 16a and the dark output line 16b have associated with them parasitic capacitances C.sub.HS and C.sub.HD. One end of the signal output line 16a and the dark output line 16b is connected to the buffer amplifier 17b and 17a, respectively.
The other ends of the signal output line 16a and the dark output line 16b are connected respectively to the drains of the horizontal read MOS transistors TR.sub.HS and TR.sub.HD which reset the residual video signal. When a drive pulse signal .PHI.RSH sent from a drive pulse generating circuit 18 is supplied to the gate electrodes of these horizontal read MOS transistors TR.sub.HS and TR.sub.HD via a clock line 18a, the horizontal read MOS transistors TR.sub.HS and TR.sub.HD operate.
The gate electrodes of the horizontal read selection MOS transistors TH.sub.S1 and TH.sub.D1 and the gate electrodes of the horizontal read selection MOS transistors TH.sub.S2 and TH.sub.D2 are connected in common, respectively, to the horizontal selection signal line 19a and the horizontal selection signal line 19b, horizontal reading being controlled by the drive pulses .PHI.H1 and .PHI.H2 which are sent from the horizontal scan circuit 6.
A drive pulse .PHI.TS which is sent from the drive pulse generating circuit 14 is supplied, via an light signal line 14a, to each of gate electrodes of light signal output transmitting MOS transistors TS.sub.1 and TS.sub.2, and a drive pulse .PHI.TD which is sent from the drive pulse generating circuit 15 is supplied, via an light signal line 14b, to each of gate electrodes of dark output transmitting MOS transistors TD.sub.1 and TD.sub.2. By means of these drive pulses .PHI.TS and .PHI.TD, light signal output transmitting MOS transistors TS.sub.1 and TS.sub.2 and dark output transmitting MOS transistors TD.sub.1 and TD.sub.2 are alternately operated in a prescribed sequence.
One each of the vertical source lines 2a and 2b is connected at each column to the drains of the resetting MOS transistors TR.sub.V1 and TR.sub.V2 and also to the regulated power supplies 22a and 22b, the sources of each of the resetting MOS transistors TR.sub.V1 and TR.sub.V2 being connected to ground, and the power supplies 22a and 22b supplying the power supply voltage VC.
The gate electrodes of the resetting MOS transistors TR.sub.V1 and TR.sub.V2 are connected to the drive pulse generating circuit 21 via the clock line 21a. When the drive pulse .PHI.RSV, which is sent from the drive pulse generating circuit 21, is supplied to the gate electrodes of the resetting MOS transistors TR.sub.V1 and TR.sub.V2, these resetting MOS transistors TR.sub.V1 and TR.sub.V2 operate, the vertical source lines 2a and 2b, the light signal output storage capacitors CS.sub.1 and CS.sub.2, and the dark output storage capacitors CD.sub.1 and CD.sub.2 are reset.